Computer networks are an increasingly important part of both private and business environments. Computing devices such as workstations, personal computers, server computers, storage devices, firewalls and other computing devices function as nodes of a network with at least one network element connecting the computing devices. The various nodes transmit and/or receive various kinds of information over the network. Computing devices and users are demanding higher communication speeds across networks as more and more information flows across the various networks. The introduction of new technologies will likely load down networks even more.
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many shared bus systems suffer from drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by many systems is a front side bus (FSB), which may typically interconnect one or more processors and a system controller.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
The latency of such a system acts as a self limiter of the overall bandwidth. The packet information must reside in memory during the round trip from the source node to the target node and the return of an acknowledge accepting receipt of the information. The current state of the art requires a software driver to pole for a completed transaction. By this mechanism a CPU and the bus associated with it will be dedicated to looping in a tight wait loop until the transaction is complete. This wait loop can be devastating to a multi-processor system. The processor bus is constantly tied-up with queries on the status of the packet.
Thus, a need still remains for a computer system with coherent interconnect. In view of the increasing dependence on clustered compute resources and multi-processor machines, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.